1 -------------------------------------------------------------------------- 2 -- 3 -- Copyright (C) 1993, Peter J. Ashenden 4 -- Mail: Dept. Computer Science 5 -- University of Adelaide, SA 5005, Australia 6 -- e-mail: petera@cs.adelaide.edu.au 7 -- 8 -- This program is free software; you can redistribute it and/or modify 9 -- it under the terms of the GNU General Public License as published by 10 -- the Free Software Foundation; either version 1, or (at your option) 11 -- any later version. 12 -- 13 -- This program is distributed in the hope that it will be useful, 14 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 15 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 -- GNU General Public License for more details. 17 -- 18 -- You should have received a copy of the GNU General Public License 19 -- along with this program; if not, write to the Free Software 20 -- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 -- 22 -------------------------------------------------------------------------- 23 -- 24 -- $RCSfile: dlx_test_rtl.vhdl,v $ $Revision: 1.1 $ $Date: 2000/05/08 14:36:48 $ 25 -- 26 -------------------------------------------------------------------------- 27 -- 28 -- Configuration of DLX test bench using register transfer level 29 -- architecture of DLX processor. 30 -- 31 32 33 configuration dlx_test_rtl of dlx_test is 34 35 for bench 36 37 for cg : clock_gen 38 use entity work.clock_gen(behaviour) 39 generic map (Tpw => 8 ns, Tps => 2 ns); 40 end for; 41 42 for mem : memory 43 use entity work.memory(behaviour) 44 generic map (mem_size => 65536, 45 Tac1 => 95 ns, Tacb => 35 ns, Tpd_clk_out => 2 ns); 46 end for; 47 48 for bus_monitor : dlx_bus_monitor 49 use entity work.dlx_bus_monitor(behaviour) 50 generic map (enable => true, verbose => true, tag => "bus monitor"); 51 end for; 52 53 for proc : dlx 54 use entity work.dlx(rtl) 55 generic map (Tpd_clk_out => 2 ns, debug => true, tag => "proc"); 56 for rtl 57 for all : alu 58 use entity work.alu(behaviour) 59 generic map (Tpd => 4 ns); 60 end for; 61 for all : reg_file 62 use entity work.reg_file(behaviour) 63 generic map (Tac => 4 ns); 64 end for; 65 for all : latch 66 use entity work.latch(behaviour) 67 generic map (Tpd => 2 ns); 68 end for; 69 for all : reg_1_out 70 use entity work.reg_1_out(behaviour) 71 generic map (Tpd => 2 ns); 72 end for; 73 for all : reg_2_out 74 use entity work.reg_2_out(behaviour) 75 generic map (Tpd => 2 ns); 76 end for; 77 for all : reg_2_1_out 78 use entity work.reg_2_1_out(behaviour) 79 generic map (Tpd => 2 ns); 80 end for; 81 for all : reg_3_out 82 use entity work.reg_3_out(behaviour) 83 generic map (Tpd => 2 ns); 84 end for; 85 for all : mux2 86 use entity work.mux2(behaviour) 87 generic map (Tpd => 1 ns); 88 end for; 89 for all : ir 90 use entity work.ir(behaviour) 91 generic map (Tpd => 2 ns); 92 end for; 93 for the_controller : controller 94 use entity work.controller(behaviour) 95 generic map (Tpd_clk_ctrl => 2 ns, Tpd_clk_const => 4 ns, 96 debug => true); 97 end for; 98 end for; -- rtl of dlx 99 end for; -- proc : dlx 100 101 end for; -- bench of dlx_test 102 103 end dlx_test_rtl; 104
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