dlx/dlx_bus_monitor-behaviour.vhdl

    1 --------------------------------------------------------------------------
    2 --
    3 --  Copyright (C) 1993, Peter J. Ashenden
    4 --  Mail:       Dept. Computer Science
    5 --              University of Adelaide, SA 5005, Australia
    6 --  e-mail:     petera@cs.adelaide.edu.au
    7 --
    8 --  This program is free software; you can redistribute it and/or modify
    9 --  it under the terms of the GNU General Public License as published by
   10 --  the Free Software Foundation; either version 1, or (at your option)
   11 --  any later version.
   12 --
   13 --  This program is distributed in the hope that it will be useful,
   14 --  but WITHOUT ANY WARRANTY; without even the implied warranty of
   15 --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   16 --  GNU General Public License for more details.
   17 --
   18 --  You should have received a copy of the GNU General Public License
   19 --  along with this program; if not, write to the Free Software
   20 --  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
   21 --
   22 --------------------------------------------------------------------------
   23 --
   24 --  $RCSfile: dlx_bus_monitor-behaviour.vhdl,v $  $Revision: 1.1 $  $Date: 2000/05/08 14:36:48 $
   25 --
   26 --------------------------------------------------------------------------
   27 --
   28 --  Behavioural architecture of DLX bus monitor
   29 --
   30 
   31 
   32 use std.textio.all,
   33     work.dlx_instr.all,
   34     work.images.image_hex;
   35 
   36 
   37 architecture behaviour of dlx_bus_monitor is
   38 
   39 begin
   40 
   41   monitor : if enable generate
   42 
   43     enabled_monitor : process
   44 
   45       variable write_command, instr_fetch : boolean;
   46       variable L : line;
   47 
   48     begin
   49       monitor_loop : loop
   50         --
   51         -- wait for a command, valid on leading edge of phi2
   52         --
   53         wait until phi2 = '1' and mem_enable = '1';
   54         --
   55         -- capture the command information
   56         --
   57         write_command := write_enable = '1';
   58         instr_fetch := ifetch = '1';
   59         write(L, tag);
   60         write(L, string'(": "));
   61         if write_command then
   62           write(L, string'("D-write to "));
   63         elsif instr_fetch then
   64           write(L, string'("I-fetch from "));
   65         else
   66           write(L, string'("D-read from "));
   67         end if;
   68         write(L, image_hex(a));
   69         if verbose then
   70           case width is
   71             when width_word =>
   72               write(L, string'(", word"));
   73             when width_halfword =>
   74               write(L, string'(", halfword"));
   75             when width_byte =>
   76               write(L, string'(", byte"));
   77           end case;
   78           if burst = '1' then
   79             write(L, string'(", burst "));
   80           else
   81             write(L, string'(", single "));
   82           end if;
   83           writeline(output, L);
   84         else
   85           if not instr_fetch then
   86             write(L, string'(", data"));
   87           else
   88             writeline(output, L);
   89           end if;
   90         end if;
   91         --
   92         burst_loop : loop
   93           if write_command then
   94             if verbose then
   95               write(L, tag);
   96               write(L, string'(": Write data "));
   97               write(L, image_hex(d));
   98               writeline(output, L);
   99             else
  100               write(L, ' ');
  101               write(L, image_hex(d));
  102             end if;
  103           end if;
  104           -- wait for the response from memory
  105           loop
  106             wait until phi2 = '0';
  107             if reset = '1' then
  108               exit monitor_loop;
  109             end if;
  110             exit when ready = '1';
  111           end loop;
  112           if write_command then
  113             if verbose then
  114               write(L, tag);
  115               write(L, string'(": Ready"));
  116               writeline(output, L);
  117             end if;
  118           elsif instr_fetch then
  119             if verbose then
  120               write(L, tag);
  121               write(L, string'(": Ready, instruction "));
  122               write(L, image_hex(d));
  123               write(L, string'(" [ "));
  124               write_instr(L, d);
  125               write(L, string'(" ]"));
  126               writeline(output, L);
  127             else                         --  brief instruction fetch
  128               write(L, tag);
  129               write(L, string'(":   "));
  130               write(L, image_hex(d));
  131               write(L, string'(" [ "));
  132               write_instr(L, d);
  133               write(L, string'(" ]"));
  134               writeline(output, L);
  135             end if;
  136           else                           --  data fetch
  137             if verbose then
  138               write(L, tag);
  139               write(L, string'(": Ready, data "));
  140               write(L, image_hex(d));
  141               writeline(output, L);
  142             else                         --  brief data fetch
  143               write(L, ' ');
  144               write(L, image_hex(d));
  145             end if;
  146           end if;
  147           exit burst_loop when burst = '0';
  148         end loop burst_loop;
  149         --
  150         if not verbose and not instr_fetch then
  151           writeline(output, L);
  152         end if;
  153       end loop monitor_loop;
  154       --
  155       -- get here when reset is asserted
  156       --
  157       assert reset = '1'
  158         report "reset code reached with reset = '0'" severity error;
  159       write(L, string'("DLX_bus_monitor: Reset"));
  160       writeline(output, L);
  161       wait until phi2 = '0' and reset = '0';
  162       write(L, string'("DLX_bus_monitor: End Reset"));
  163       writeline(output, L);
  164       --
  165       -- process monitor now starts again from beginning
  166       --
  167     end process enabled_monitor;
  168 
  169   end generate;
  170 
  171 end behaviour;
  172 

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