1 -------------------------------------------------------------------------- 2 -- 3 -- Copyright (C) 1993, Peter J. Ashenden 4 -- Mail: Dept. Computer Science 5 -- University of Adelaide, SA 5005, Australia 6 -- e-mail: petera@cs.adelaide.edu.au 7 -- 8 -- This program is free software; you can redistribute it and/or modify 9 -- it under the terms of the GNU General Public License as published by 10 -- the Free Software Foundation; either version 1, or (at your option) 11 -- any later version. 12 -- 13 -- This program is distributed in the hope that it will be useful, 14 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 15 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 -- GNU General Public License for more details. 17 -- 18 -- You should have received a copy of the GNU General Public License 19 -- along with this program; if not, write to the Free Software 20 -- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 -- 22 -------------------------------------------------------------------------- 23 -- 24 -- $RCSfile: dlx_bus_monitor.vhdl,v $ $Revision: 1.1 $ $Date: 2000/05/08 14:36:48 $ 25 -- 26 -------------------------------------------------------------------------- 27 -- 28 -- Entity declaration of DLX bus monitor 29 -- 30 31 32 use work.dlx_types.all, 33 work.mem_types.all; 34 35 entity dlx_bus_monitor is 36 generic (enable : boolean := true; -- enable monitoring 37 verbose : boolean := true; -- verbose vs brief info 38 tag : string := ""); 39 port (phi1, phi2 : in bit; -- 2-phase non-overlapping clocks 40 reset : in bit; -- synchronous reset 41 a : in dlx_address; -- address bus 42 d : in dlx_word; -- data bus 43 halt : in bit; -- halt indicator 44 width : in mem_width; -- byte/haldword/word indicator 45 write_enable : in bit; -- selects read or write cycle 46 burst : in bit := '0'; -- indicates more to come in burst 47 mem_enable : in bit; -- starts memory cycle 48 ifetch : in bit; -- indicates instruction fetch 49 ready : in bit); -- status from memory system 50 end dlx_bus_monitor; 51
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