dlx/ir-behaviour.vhdl

    1 --------------------------------------------------------------------------
    2 --
    3 --  Copyright (C) 1993, Peter J. Ashenden
    4 --  Mail:	Dept. Computer Science
    5 --		University of Adelaide, SA 5005, Australia
    6 --  e-mail:	petera@cs.adelaide.edu.au
    7 --
    8 --  This program is free software; you can redistribute it and/or modify
    9 --  it under the terms of the GNU General Public License as published by
   10 --  the Free Software Foundation; either version 1, or (at your option)
   11 --  any later version.
   12 --
   13 --  This program is distributed in the hope that it will be useful,
   14 --  but WITHOUT ANY WARRANTY; without even the implied warranty of
   15 --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   16 --  GNU General Public License for more details.
   17 --
   18 --  You should have received a copy of the GNU General Public License
   19 --  along with this program; if not, write to the Free Software
   20 --  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
   21 --
   22 --------------------------------------------------------------------------
   23 --
   24 --  $RCSfile: ir-behaviour.vhdl,v $  $Revision: 1.1 $  $Date: 2000/05/08 14:36:48 $
   25 --
   26 --------------------------------------------------------------------------
   27 --
   28 --  Behavioural architecture of instruction register.
   29 --
   30 
   31 
   32 use work.dlx_instr.all;
   33 
   34 architecture behaviour of ir is
   35 
   36 begin
   37 
   38   reg: process (d, latch_en, immed_sel1, immed_sel2,
   39                 immed_unsigned1, immed_unsigned2, immed_en1, immed_en2)
   40 
   41     variable latched_instr : dlx_word;
   42 
   43     use work.bv_arithmetic.bv_zext, work.bv_arithmetic.bv_sext;
   44 
   45   begin
   46     if latch_en = '1' then
   47       latched_instr := d;
   48       ir_out <= latched_instr after Tpd;
   49     end if;
   50     --
   51     if immed_en1 = '1' then
   52       if immed_sel1 = immed_size_16 then
   53         if immed_unsigned1 = '1' then
   54           immed_q1 <= bv_zext(latched_instr(16 to 31), 32) after Tpd;
   55         else
   56           immed_q1 <= bv_sext(latched_instr(16 to 31), 32) after Tpd;
   57         end if;
   58       else -- immed_sel1 = immed_size_26
   59         if immed_unsigned1 = '1' then
   60           immed_q1 <= bv_zext(latched_instr(6 to 31), 32) after Tpd;
   61         else
   62           immed_q1 <= bv_sext(latched_instr(6 to 31), 32) after Tpd;
   63         end if;
   64       end if;
   65     else
   66       immed_q1 <= null after Tpd;
   67     end if;
   68     --
   69     if immed_en2 = '1' then
   70       if immed_sel2 = immed_size_16 then
   71         if immed_unsigned2 = '1' then
   72           immed_q2 <= bv_zext(latched_instr(16 to 31), 32) after Tpd;
   73         else
   74           immed_q2 <= bv_sext(latched_instr(16 to 31), 32) after Tpd;
   75         end if;
   76       else -- immed_sel2 = immed_size_26
   77         if immed_unsigned2 = '1' then
   78           immed_q2 <= bv_zext(latched_instr(6 to 31), 32) after Tpd;
   79         else
   80           immed_q2 <= bv_sext(latched_instr(6 to 31), 32) after Tpd;
   81         end if;
   82       end if;
   83     else
   84       immed_q2 <= null after Tpd;
   85     end if;
   86   end process reg;
   87 
   88 end behaviour;
   89 

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