1 --------------------------------------------------------------------------
2 --
3 -- Copyright (C) 1993, Peter J. Ashenden
4 -- Mail: Dept. Computer Science
5 -- University of Adelaide, SA 5005, Australia
6 -- e-mail: petera@cs.adelaide.edu.au
7 --
8 -- This program is free software; you can redistribute it and/or modify
9 -- it under the terms of the GNU General Public License as published by
10 -- the Free Software Foundation; either version 1, or (at your option)
11 -- any later version.
12 --
13 -- This program is distributed in the hope that it will be useful,
14 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
15 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 -- GNU General Public License for more details.
17 --
18 -- You should have received a copy of the GNU General Public License
19 -- along with this program; if not, write to the Free Software
20 -- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 --
22 --------------------------------------------------------------------------
23 --
24 -- $RCSfile: memory.vhdl,v $ $Revision: 1.1 $ $Date: 2000/05/08 14:36:48 $
25 --
26 --------------------------------------------------------------------------
27 --
28 -- Entity declaration for memory model
29 --
30
31
32 use work.dlx_types.all, work.mem_types.all;
33
34 entity memory is
35
36 generic (mem_size : positive; -- size in bytes (multiple of 4)
37 Tac1 : Time; -- access time 1st cycle (read or write)
38 Tacb : Time; -- access time burst (read or write)
39 Tpd_clk_out : Time; -- clock to output delay
40 tag : string := "";
41 origin_x, origin_y : real := 0.0);
42
43 port (phi1, phi2 : in bit; -- 2-phase non-overlapping clocks
44 a : in dlx_address; -- byte address: a(0) is lsb
45 d : inout dlx_word_bus bus; -- bidirectional data bus: d(0) is msb
46 width : in mem_width; -- byte/haldword/word indicator
47 write_enable : in bit; -- selects read or write cycle
48 burst : in bit := '0'; -- indicates more to come in burst
49 -- can be left open
50 -- for non-burst client
51 mem_enable : in bit; -- starts memory cycle
52 ready : out bit); -- status from memory system
53
54 end memory;
55
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