1 -------------------------------------------------------------------------- 2 -- 3 -- Copyright (C) 1993, Peter J. Ashenden 4 -- Mail: Dept. Computer Science 5 -- University of Adelaide, SA 5005, Australia 6 -- e-mail: petera@cs.adelaide.edu.au 7 -- 8 -- This program is free software; you can redistribute it and/or modify 9 -- it under the terms of the GNU General Public License as published by 10 -- the Free Software Foundation; either version 1, or (at your option) 11 -- any later version. 12 -- 13 -- This program is distributed in the hope that it will be useful, 14 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 15 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 -- GNU General Public License for more details. 17 -- 18 -- You should have received a copy of the GNU General Public License 19 -- along with this program; if not, write to the Free Software 20 -- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 -- 22 -------------------------------------------------------------------------- 23 -- 24 -- $RCSfile: reg_1_out.vhdl,v $ $Revision: 1.1 $ $Date: 2000/05/08 14:36:48 $ 25 -- 26 -------------------------------------------------------------------------- 27 -- 28 -- Entity declaration for register with one tri-state output. 29 -- 30 31 32 use work.dlx_types.all; 33 34 entity reg_1_out is 35 generic (Tpd : Time; 36 tag : string := ""; 37 origin_x, origin_y : real := 0.0); 38 port (d : in dlx_word; 39 q : out dlx_word_bus bus; 40 latch_en : in bit; 41 out_en : in bit); 42 end reg_1_out; 43
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