1 --------------------------------------------------------------------------
2 --
3 -- Copyright (C) 1993, Peter J. Ashenden
4 -- Mail: Dept. Computer Science
5 -- University of Adelaide, SA 5005, Australia
6 -- e-mail: petera@cs.adelaide.edu.au
7 --
8 -- This program is free software; you can redistribute it and/or modify
9 -- it under the terms of the GNU General Public License as published by
10 -- the Free Software Foundation; either version 1, or (at your option)
11 -- any later version.
12 --
13 -- This program is distributed in the hope that it will be useful,
14 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
15 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 -- GNU General Public License for more details.
17 --
18 -- You should have received a copy of the GNU General Public License
19 -- along with this program; if not, write to the Free Software
20 -- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 --
22 --------------------------------------------------------------------------
23 --
24 -- $RCSfile: dlx-rtl.vhdl,v $ $Revision: 1.1 $ $Date: 2000/05/08 14:36:48 $
25 --
26 --------------------------------------------------------------------------
27 --
28 -- Register transfer level architecture of DLX processor.
29 --
30
31
32 use std.textio.all,
33 work.images.image_hex,
34 work.bv_arithmetic.all,
35 work.dlx_instr.all,
36 work.alu_types.all;
37
38
39 architecture rtl of dlx is
40
41 component alu
42 port (s1 : in dlx_word;
43 s2 : in dlx_word;
44 result : out dlx_word;
45 latch_en : in bit;
46 func : in alu_func;
47 zero, negative, overflow : out bit);
48 end component;
49
50 component reg_file
51 port (a1 : in dlx_reg_addr; -- port1 address
52 q1 : out dlx_word; -- port1 read data
53 a2 : in dlx_reg_addr; -- port2 address
54 q2 : out dlx_word; -- port2 read data
55 a3 : in dlx_reg_addr; -- port3 address
56 d3 : in dlx_word; -- port3 write data
57 write_en : in bit); -- port3 write enable
58 end component;
59
60 component latch
61 port (d : in dlx_word;
62 q : out dlx_word;
63 latch_en : in bit);
64 end component;
65
66 component reg_1_out
67 port (d : in dlx_word;
68 q : out dlx_word_bus bus;
69 latch_en : in bit;
70 out_en : in bit);
71 end component;
72
73 component reg_2_out
74 port (d : in dlx_word;
75 q1, q2 : out dlx_word_bus bus;
76 latch_en : in bit;
77 out_en1, out_en2 : in bit);
78 end component;
79
80 component reg_3_out
81 port (d : in dlx_word;
82 q1, q2, q3 : out dlx_word_bus bus;
83 latch_en : in bit;
84 out_en1, out_en2, out_en3 : in bit);
85 end component;
86
87 component reg_2_1_out
88 port (d : in dlx_word;
89 q1, q2 : out dlx_word_bus bus;
90 q3 : out dlx_word;
91 latch_en : in bit;
92 out_en1, out_en2 : in bit);
93 end component;
94
95 component mux2
96 port (i0, i1 : in dlx_word;
97 y : out dlx_word;
98 sel : in bit);
99 end component;
100
101 component ir
102 port (d : in dlx_word; -- instruction input from memory
103 immed_q1, immed_q2 : out dlx_word_bus bus;
104 ir_out : out dlx_word; -- instruction output to control
105 latch_en : in bit;
106 immed_sel1, immed_sel2 : in immed_size; -- select 16-bit or 26-bit immed
107 immed_unsigned1, immed_unsigned2 : in bit; -- extend immed unsigned/signed
108 immed_en1, immed_en2 : in bit); -- enable immed const outputs
109 end component;
110
111 component controller
112 port (phi1, phi2 : in bit;
113 reset : in bit;
114 halt : out bit;
115 width : out mem_width;
116 write_enable : out bit;
117 mem_enable : out bit;
118 ifetch : out bit;
119 ready : in bit;
120 alu_latch_en : out bit;
121 alu_function : out alu_func;
122 alu_zero, alu_negative, alu_overflow : in bit;
123 reg_s1_addr, reg_s2_addr, reg_dest_addr : out dlx_reg_addr;
124 reg_write : out bit;
125 c_latch_en : out bit;
126 a_latch_en, a_out_en : out bit;
127 b_latch_en, b_out_en : out bit;
128 temp_latch_en, temp_out_en1, temp_out_en2 : out bit;
129 iar_latch_en, iar_out_en1, iar_out_en2 : out bit;
130 pc_latch_en, pc_out_en1, pc_out_en2 : out bit;
131 mar_latch_en, mar_out_en1, mar_out_en2 : out bit;
132 mem_addr_mux_sel : out bit;
133 mdr_latch_en, mdr_out_en1, mdr_out_en2, mdr_out_en3 : out bit;
134 mdr_mux_sel : out bit;
135 ir_latch_en : out bit;
136 ir_immed_sel1, ir_immed_sel2 : out immed_size;
137 ir_immed_unsigned1, ir_immed_unsigned2 : out bit;
138 ir_immed_en1, ir_immed_en2 : out bit;
139 current_instruction : in dlx_word;
140 const1, const2 : out dlx_word_bus bus);
141 end component;
142
143 signal s1_bus, s2_bus : dlx_word_bus;
144 signal dest_bus : dlx_word;
145 signal alu_latch_en : bit;
146 signal alu_function : alu_func;
147 signal alu_zero, alu_negative, alu_overflow : bit;
148 signal reg_s1_addr, reg_s2_addr, reg_dest_addr : dlx_reg_addr;
149 signal reg_file_out1, reg_file_out2, reg_file_in : dlx_word;
150 signal reg_write : bit;
151 signal a_out_en, a_latch_en : bit;
152 signal b_out_en, b_latch_en : bit;
153 signal c_latch_en : bit;
154 signal temp_out_en1, temp_out_en2, temp_latch_en : bit;
155 signal iar_out_en1, iar_out_en2, iar_latch_en : bit;
156 signal pc_out_en1, pc_out_en2, pc_latch_en : bit;
157 signal pc_to_mem : dlx_word;
158 signal mar_out_en1, mar_out_en2, mar_latch_en : bit;
159 signal mar_to_mem : dlx_word;
160 signal mem_addr_mux_sel : bit;
161 signal mdr_out_en1, mdr_out_en2, mdr_out_en3, mdr_latch_en : bit;
162 signal mdr_in : dlx_word;
163 signal mdr_mux_sel : bit;
164 signal current_instruction : dlx_word;
165 signal ir_latch_en : bit;
166 signal ir_immed_sel1, ir_immed_sel2 : immed_size;
167 signal ir_immed_unsigned1, ir_immed_unsigned2 : bit;
168 signal ir_immed_en1, ir_immed_en2 : bit;
169
170 begin
171
172 the_alu : alu
173 port map (s1 => s1_bus, s2 => s2_bus, result => dest_bus,
174 latch_en => alu_latch_en, func => alu_function,
175 zero => alu_zero, negative => alu_negative, overflow => alu_overflow);
176
177 the_reg_file : reg_file
178 port map (a1 => reg_s1_addr, q1 => reg_file_out1,
179 a2 => reg_s2_addr, q2 => reg_file_out2,
180 a3 => reg_dest_addr, d3 => reg_file_in,
181 write_en => reg_write);
182
183 c_reg : latch
184 port map (d => dest_bus, q => reg_file_in, latch_en => c_latch_en);
185
186 a_reg : reg_1_out
187 port map (d => reg_file_out1, q => s1_bus,
188 latch_en => a_latch_en, out_en => a_out_en);
189
190 b_reg : reg_1_out
191 port map (d => reg_file_out2, q => s2_bus,
192 latch_en => b_latch_en, out_en => b_out_en);
193
194 temp_reg : reg_2_out
195 port map (d => dest_bus, q1 => s1_bus, q2 => s2_bus,
196 latch_en => temp_latch_en,
197 out_en1 => temp_out_en1, out_en2 => temp_out_en2);
198
199 iar_reg : reg_2_out
200 port map (d => dest_bus, q1 => s1_bus, q2 => s2_bus,
201 latch_en => iar_latch_en,
202 out_en1 => iar_out_en1, out_en2 => iar_out_en2);
203
204 pc_reg : reg_2_1_out
205 port map (d => dest_bus, q1 => s1_bus, q2 => s2_bus, q3 => pc_to_mem,
206 latch_en => pc_latch_en,
207 out_en1 => pc_out_en1, out_en2 => pc_out_en2);
208
209 mar_reg : reg_2_1_out
210 port map (d => dest_bus, q1 => s1_bus, q2 => s2_bus, q3 => mar_to_mem,
211 latch_en => mar_latch_en,
212 out_en1 => mar_out_en1, out_en2 => mar_out_en2);
213
214 mem_addr_mux : mux2
215 port map (i0 => pc_to_mem, i1 => mar_to_mem, y => a,
216 sel => mem_addr_mux_sel);
217
218 mdr_reg : reg_3_out
219 port map (d => mdr_in, q1 => s1_bus, q2 => s2_bus, q3 => d,
220 latch_en => mdr_latch_en,
221 out_en1 => mdr_out_en1, out_en2 => mdr_out_en2,
222 out_en3 => mdr_out_en3);
223
224 mdr_mux : mux2
225 port map (i0 => dest_bus, i1 => d, y => mdr_in,
226 sel => mdr_mux_sel);
227
228 instr_reg : ir
229 port map (d => d, immed_q1 => s1_bus, immed_q2 => s2_bus,
230 ir_out => current_instruction,
231 latch_en => ir_latch_en,
232 immed_sel1 => ir_immed_sel1, immed_sel2 => ir_immed_sel2,
233 immed_unsigned1 => ir_immed_unsigned1,
234 immed_unsigned2 => ir_immed_unsigned2,
235 immed_en1 => ir_immed_en1, immed_en2 => ir_immed_en2);
236
237 the_controller : controller
238 port map (phi1, phi2, reset, halt,
239 width, write_enable, mem_enable, ifetch, ready,
240 alu_latch_en, alu_function, alu_zero, alu_negative, alu_overflow,
241 reg_s1_addr, reg_s2_addr, reg_dest_addr, reg_write,
242 c_latch_en, a_latch_en, a_out_en, b_latch_en, b_out_en,
243 temp_latch_en, temp_out_en1, temp_out_en2,
244 iar_latch_en, iar_out_en1, iar_out_en2,
245 pc_latch_en, pc_out_en1, pc_out_en2,
246 mar_latch_en, mar_out_en1, mar_out_en2, mem_addr_mux_sel,
247 mdr_latch_en, mdr_out_en1, mdr_out_en2,
248 mdr_out_en3, mdr_mux_sel,
249 ir_latch_en, ir_immed_sel1, ir_immed_sel2,
250 ir_immed_unsigned1, ir_immed_unsigned2, ir_immed_en1, ir_immed_en2,
251 current_instruction, s1_bus, s2_bus);
252
253 debug_s1 : if debug generate
254 s1_monitor : process (s1_bus)
255 variable L : line;
256 begin
257 write(L, tag);
258 write(L, string'(" s1_monitor: "));
259 write(L, image_hex(s1_bus));
260 writeline(output, L);
261 end process s1_monitor;
262 end generate;
263
264 debug_s2 : if debug generate
265 s2_monitor : process (s2_bus)
266 variable L : line;
267 begin
268 write(L, tag);
269 write(L, string'(" s2_monitor: "));
270 write(L, image_hex(s2_bus));
271 writeline(output, L);
272 end process s2_monitor;
273 end generate;
274
275 debug_dest : if debug generate
276 dest_monitor : process (dest_bus)
277 variable L : line;
278 begin
279 write(L, tag);
280 write(L, string'(" dest_monitor: "));
281 write(L, image_hex(dest_bus));
282 writeline(output, L);
283 end process dest_monitor;
284 end generate;
285
286 end rtl;
287
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