1 --------------------------------------------------------------------------
2 --
3 -- Copyright (C) 1993, Peter J. Ashenden
4 -- Mail: Dept. Computer Science
5 -- University of Adelaide, SA 5005, Australia
6 -- e-mail: petera@cs.adelaide.edu.au
7 --
8 -- This program is free software; you can redistribute it and/or modify
9 -- it under the terms of the GNU General Public License as published by
10 -- the Free Software Foundation; either version 1, or (at your option)
11 -- any later version.
12 --
13 -- This program is distributed in the hope that it will be useful,
14 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
15 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 -- GNU General Public License for more details.
17 --
18 -- You should have received a copy of the GNU General Public License
19 -- along with this program; if not, write to the Free Software
20 -- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 --
22 --------------------------------------------------------------------------
23 --
24 -- $RCSfile: dlx_test-bench.vhdl,v $ $Revision: 1.1 $ $Date: 2000/05/08 14:36:48 $
25 --
26 --------------------------------------------------------------------------
27 --
28 -- Architecture for test bench for DLX,
29 -- consisting of clock generator, memory and bus_monitor
30 --
31
32
33 use std.textio.all,
34 work.dlx_types.all, work.mem_types.all;
35
36 architecture bench of dlx_test is
37
38 component clock_gen
39 port (phi1, phi2 : out bit;
40 reset : out bit);
41 end component;
42
43 component memory
44 port (phi1, phi2 : in bit;
45 a : in dlx_address;
46 d : inout dlx_word_bus bus;
47 width : in mem_width;
48 write_enable : in bit;
49 burst : in bit := '0';
50 mem_enable : in bit;
51 ready : out bit);
52 end component;
53
54 component dlx
55 port (phi1, phi2 : in bit; -- 2-phase non-overlapping clocks
56 reset : in bit; -- synchronous reset input
57 a : out dlx_address; -- address bus output
58 d : inout dlx_word_bus bus; -- bidirectional data bus
59 halt : out bit; -- halt indicator
60 width : out mem_width; -- byte/haldword/word indicator
61 write_enable : out bit; -- selects read or write cycle
62 mem_enable : out bit; -- starts memory cycle
63 ifetch : out bit; -- indicates instruction fetch
64 ready : in bit); -- status from memory system
65 end component;
66
67 component dlx_bus_monitor
68 port (phi1, phi2 : in bit; -- 2-phase non-overlapping clocks
69 reset : in bit; -- synchronous reset
70 a : in dlx_address; -- address bus
71 d : in dlx_word; -- data bus
72 halt : in bit; -- halt indicator
73 width : in mem_width; -- byte/haldword/word indicator
74 write_enable : in bit; -- selects read or write cycle
75 burst : in bit := '0'; -- indicates more to come in burst
76 mem_enable : in bit; -- starts memory cycle
77 ifetch : in bit; -- indicates instruction fetch
78 ready : in bit); -- status from memory system
79 end component;
80
81 signal phi1, phi2, reset : bit;
82 signal a : dlx_address;
83 signal d : dlx_word_bus bus;
84 signal halt : bit;
85 signal width : mem_width;
86 signal write_enable, mem_enable, ifetch, ready : bit;
87
88 begin
89
90 cg : clock_gen
91 port map (phi1, phi2, reset);
92
93 mem : memory
94 port map (phi1, phi2, a, d, width, write_enable, open, mem_enable, ready);
95
96 proc : dlx
97 port map (phi1, phi2, reset, a, d,
98 halt, width, write_enable, mem_enable, ifetch, ready);
99
100 bus_monitor : dlx_bus_monitor
101 port map (phi1, phi2, reset, a, d,
102 halt, width, write_enable, open, mem_enable, ifetch, ready);
103
104 end bench;
105
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