1 --------------------------------------------------------------------------
2 --
3 -- Copyright (C) 1993, Peter J. Ashenden
4 -- Mail: Dept. Computer Science
5 -- University of Adelaide, SA 5005, Australia
6 -- e-mail: petera@cs.adelaide.edu.au
7 --
8 -- This program is free software; you can redistribute it and/or modify
9 -- it under the terms of the GNU General Public License as published by
10 -- the Free Software Foundation; either version 1, or (at your option)
11 -- any later version.
12 --
13 -- This program is distributed in the hope that it will be useful,
14 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
15 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 -- GNU General Public License for more details.
17 --
18 -- You should have received a copy of the GNU General Public License
19 -- along with this program; if not, write to the Free Software
20 -- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 --
22 --------------------------------------------------------------------------
23 --
24 -- $RCSfile: clock_gen-behaviour.vhdl,v $ $Revision: 1.1 $ $Date: 2000/05/08 14:36:47 $
25 --
26 --------------------------------------------------------------------------
27 --
28 -- Behavioural architecture body for clock generator
29 --
30
31
32 architecture behaviour of clock_gen is
33
34 constant clock_period : Time := 2*(Tpw+Tps);
35
36 begin
37
38 reset_driver:
39 reset <= '1', '0' after 2*clock_period + Tpw+Tps;
40
41 clock_driver : process
42 begin
43 phi1 <= '1', '0' after Tpw;
44 phi2 <= '1' after Tpw+Tps, '0' after Tpw+Tps+Tpw;
45 wait for clock_period;
46 end process clock_driver;
47
48 end behaviour;
49
This page was generated using GHDL 0.14 (20040829) [Sokcho edition], a program written by Tristan Gingold