1 --------------------------------------------------------------------------
2 --
3 -- Copyright (C) 1993, Peter J. Ashenden
4 -- Mail: Dept. Computer Science
5 -- University of Adelaide, SA 5005, Australia
6 -- e-mail: petera@cs.adelaide.edu.au
7 --
8 -- This program is free software; you can redistribute it and/or modify
9 -- it under the terms of the GNU General Public License as published by
10 -- the Free Software Foundation; either version 1, or (at your option)
11 -- any later version.
12 --
13 -- This program is distributed in the hope that it will be useful,
14 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
15 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 -- GNU General Public License for more details.
17 --
18 -- You should have received a copy of the GNU General Public License
19 -- along with this program; if not, write to the Free Software
20 -- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 --
22 --------------------------------------------------------------------------
23 --
24 -- $RCSfile: reg_file-behaviour.vhdl,v $ $Revision: 1.1 $ $Date: 2000/05/08 14:36:48 $
25 --
26 --------------------------------------------------------------------------
27 --
28 -- Behavioural architecture of register file.
29 --
30
31
32 architecture behaviour of reg_file is
33
34 begin
35
36 reg: process (a1, a2, a3, d3, write_en)
37
38 use work.bv_arithmetic.bv_to_natural;
39
40 constant all_zeros : dlx_word := X"0000_0000";
41
42 type register_array is array (reg_index range 1 to 31) of dlx_word;
43
44 variable register_file : register_array;
45 variable reg_index1, reg_index2, reg_index3 : reg_index;
46
47 begin
48 -- do write first if enabled
49 --
50 if write_en = '1' then
51 reg_index3 := bv_to_natural(a3);
52 if reg_index3 /= 0 then
53 register_file(reg_index3) := d3;
54 end if;
55 end if;
56 --
57 -- read port 1
58 --
59 reg_index1 := bv_to_natural(a1);
60 if reg_index1 /= 0 then
61 q1 <= register_file(reg_index1) after Tac;
62 else
63 q1 <= all_zeros after Tac;
64 end if;
65 --
66 -- read port 2
67 --
68 reg_index2 := bv_to_natural(a2);
69 if reg_index2 /= 0 then
70 q2 <= register_file(reg_index2) after Tac;
71 else
72 q2 <= all_zeros after Tac;
73 end if;
74 end process reg;
75
76 end behaviour;
77
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