1 --------------------------------------------------------------------------
2 --
3 -- Copyright (C) 1993, Peter J. Ashenden
4 -- Mail: Dept. Computer Science
5 -- University of Adelaide, SA 5005, Australia
6 -- e-mail: petera@cs.adelaide.edu.au
7 --
8 -- This program is free software; you can redistribute it and/or modify
9 -- it under the terms of the GNU General Public License as published by
10 -- the Free Software Foundation; either version 1, or (at your option)
11 -- any later version.
12 --
13 -- This program is distributed in the hope that it will be useful,
14 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
15 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 -- GNU General Public License for more details.
17 --
18 -- You should have received a copy of the GNU General Public License
19 -- along with this program; if not, write to the Free Software
20 -- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 --
22 --------------------------------------------------------------------------
23 --
24 -- $RCSfile: reg_2_1_out-behaviour.vhdl,v $ $Revision: 1.1 $ $Date: 2000/05/08 14:36:48 $
25 --
26 --------------------------------------------------------------------------
27 --
28 -- Behavioural architecture of register with two tri-state
29 -- outputs and one ordinary output.
30 --
31
32
33 architecture behaviour of reg_2_1_out is
34
35 begin
36
37 reg: process (d, latch_en, out_en1, out_en2)
38
39 variable latched_value : dlx_word;
40
41 begin
42 if latch_en = '1' then
43 latched_value := d;
44 end if;
45 if out_en1 = '1' then
46 q1 <= latched_value after Tpd;
47 else
48 q1 <= null after Tpd;
49 end if;
50 if out_en2 = '1' then
51 q2 <= latched_value after Tpd;
52 else
53 q2 <= null after Tpd;
54 end if;
55 q3 <= latched_value after Tpd;
56 end process reg;
57
58 end behaviour;
59
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