1 --------------------------------------------------------------------------
2 --
3 -- Copyright (C) 1993, Peter J. Ashenden
4 -- Mail: Dept. Computer Science
5 -- University of Adelaide, SA 5005, Australia
6 -- e-mail: petera@cs.adelaide.edu.au
7 --
8 -- This program is free software; you can redistribute it and/or modify
9 -- it under the terms of the GNU General Public License as published by
10 -- the Free Software Foundation; either version 1, or (at your option)
11 -- any later version.
12 --
13 -- This program is distributed in the hope that it will be useful,
14 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
15 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 -- GNU General Public License for more details.
17 --
18 -- You should have received a copy of the GNU General Public License
19 -- along with this program; if not, write to the Free Software
20 -- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 --
22 --------------------------------------------------------------------------
23 --
24 -- $RCSfile: controller.vhdl,v $ $Revision: 1.1 $ $Date: 2000/05/08 14:36:47 $
25 --
26 --------------------------------------------------------------------------
27 --
28 -- Entity declaration for DLX control section.
29 --
30
31
32 use work.dlx_types.all,
33 work.dlx_instr.all,
34 work.alu_types.all,
35 work.mem_types.all;
36
37 entity controller is
38 generic (Tpd_clk_ctrl, Tpd_clk_const : Time;
39 debug : boolean := false;
40 tag : string := "";
41 origin_x, origin_y : real := 0.0);
42 port (phi1, phi2 : in bit;
43 reset : in bit;
44 halt : out bit;
45 width : out mem_width;
46 write_enable : out bit;
47 mem_enable : out bit;
48 ifetch : out bit;
49 ready : in bit;
50 alu_latch_en : out bit;
51 alu_function : out alu_func;
52 alu_zero, alu_negative, alu_overflow : in bit;
53 reg_s1_addr, reg_s2_addr, reg_dest_addr : out dlx_reg_addr;
54 reg_write : out bit;
55 c_latch_en : out bit;
56 a_latch_en, a_out_en : out bit;
57 b_latch_en, b_out_en : out bit;
58 temp_latch_en, temp_out_en1, temp_out_en2 : out bit;
59 iar_latch_en, iar_out_en1, iar_out_en2 : out bit;
60 pc_latch_en, pc_out_en1, pc_out_en2 : out bit;
61 mar_latch_en, mar_out_en1, mar_out_en2 : out bit;
62 mem_addr_mux_sel : out bit;
63 mdr_latch_en, mdr_out_en1, mdr_out_en2, mdr_out_en3 : out bit;
64 mdr_mux_sel : out bit;
65 ir_latch_en : out bit;
66 ir_immed_sel1, ir_immed_sel2 : out immed_size;
67 ir_immed_unsigned1, ir_immed_unsigned2 : out bit;
68 ir_immed_en1, ir_immed_en2 : out bit;
69 current_instruction : in dlx_word;
70 const1, const2 : out dlx_word_bus bus);
71 end controller;
72
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