1 use work.dlx_types.all;
2
3 entity testbus_mem is
4 port (d : inout dlx_word;
5 write_enable : in bit;
6 reset : in bit;
7 clk : in bit);
8 end;
9
10 architecture behav of testbus_mem is
11 begin
12 process (clk)
13 variable m : dlx_word;
14 begin
15 if clk = '1' and clk'event then
16 if write_enable = '1' then
17 if reset = '1' then
18 m := (others => '1');
19 else
20 m := d;
21 end if;
22 else
23 d <= m;
24 end if;
25 end if;
26 end process;
27 end behav;
28
29 entity testbus is
30 end testbus;
31
32 use work.dlx_types.all;
33
34 architecture behav of testbus is
35 signal d : dlx_word_bus bus;
36 signal clk : bit;
37 signal wen : bit;
38 signal reset : bit;
39 begin
40 comp : entity work.testbus_mem
41 port map (d => d, write_enable => wen, reset => reset, clk => clk);
42
43 process
44 begin
45 clk <= '0';
46 reset <= '0';
47 wait for 1 ns;
48
49 -- read
50 wen <= '0';
51 clk <= '1';
52 wait for 1 ns;
53
54 assert d = x"0000_0000" report "bad initial value" severity failure;
55
56 -- write
57 clk <= '0';
58 wait for 1 ns;
59
60 wen <= '1';
61 d <= x"1234_5678";
62 clk <= '1';
63 wait for 1 ns;
64
65 assert d = x"1234_5678" report "bad value 1" severity failure;
66
67 clk <= '0';
68 wait for 1 ns;
69
70 wen <= '0';
71 clk <= '1';
72 wait for 1 ns;
73
74 assert d = x"1234_5678" report "bad value 2" severity failure;
75
76 wen <= '1';
77 reset <= '1';
78 d <= x"eeee_1111";
79 clk <= '0';
80 wait for 1 ns;
81 assert false report "time is 6 ns" severity note;
82
83 clk <= '1';
84 wait for 1 ns;
85
86 wen <= '0';
87 clk <= '0';
88 wait for 1 ns;
89
90 clk <= '1';
91 wait for 1 ns;
92
93 assert d = x"ffff_ffff" report "bad value 3" severity failure;
94
95 assert false report "end of test" severity note;
96 wait;
97 end process;
98 end behav;
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