1 --------------------------------------------------------------------------
2 --
3 -- Copyright (C) 1993, Peter J. Ashenden
4 -- Mail: Dept. Computer Science
5 -- University of Adelaide, SA 5005, Australia
6 -- e-mail: petera@cs.adelaide.edu.au
7 --
8 -- This program is free software; you can redistribute it and/or modify
9 -- it under the terms of the GNU General Public License as published by
10 -- the Free Software Foundation; either version 1, or (at your option)
11 -- any later version.
12 --
13 -- This program is distributed in the hope that it will be useful,
14 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
15 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 -- GNU General Public License for more details.
17 --
18 -- You should have received a copy of the GNU General Public License
19 -- along with this program; if not, write to the Free Software
20 -- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 --
22 --------------------------------------------------------------------------
23 --
24 -- $RCSfile: dlx_test_cache.vhdl,v $ $Revision: 1.1 $ $Date: 2000/05/08 14:36:48 $
25 --
26 --------------------------------------------------------------------------
27 --
28 -- Configuration of test bench for DLX and cache,
29 -- using behavioural architectures.
30 --
31
32
33 configuration dlx_test_cache of dlx_test is
34
35 for bench_cache
36
37 use work.cache_types.all;
38
39 for cg : clock_gen
40 use entity work.clock_gen(behaviour)
41 generic map (Tpw => 8 ns, Tps => 2 ns);
42 end for;
43
44 for mem : memory
45 use entity work.memory(behaviour)
46 generic map (mem_size => 65536,
47 Tac1 => 95 ns, Tacb => 35 ns, Tpd_clk_out => 2 ns);
48 end for;
49
50 for the_cache : cache
51 use entity work.cache(behaviour)
52 generic map (cache_size => 4096, line_size => 16,
53 associativity => 2, write_strategy => write_through,
54 Tpd_clk_out => 2 ns);
55 end for;
56
57 for cpu_cache_monitor : dlx_bus_monitor
58 use entity work.dlx_bus_monitor(behaviour)
59 generic map (enable => true, verbose => false, tag => "cpu cache monitor");
60 end for;
61
62 for cache_mem_monitor : dlx_bus_monitor
63 use entity work.dlx_bus_monitor(behaviour)
64 generic map (enable => true, verbose => false, tag => "cache mem monitor");
65 end for;
66
67 for proc : dlx
68 use entity work.dlx(behaviour)
69 generic map (Tpd_clk_out => 2 ns, debug => false, tag => "proc");
70 end for;
71
72 end for;
73
74 end dlx_test_cache;
75
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