1 --------------------------------------------------------------------------
2 --
3 -- Copyright (C) 1993, Peter J. Ashenden
4 -- Mail: Dept. Computer Science
5 -- University of Adelaide, SA 5005, Australia
6 -- e-mail: petera@cs.adelaide.edu.au
7 --
8 -- This program is free software; you can redistribute it and/or modify
9 -- it under the terms of the GNU General Public License as published by
10 -- the Free Software Foundation; either version 1, or (at your option)
11 -- any later version.
12 --
13 -- This program is distributed in the hope that it will be useful,
14 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
15 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 -- GNU General Public License for more details.
17 --
18 -- You should have received a copy of the GNU General Public License
19 -- along with this program; if not, write to the Free Software
20 -- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 --
22 --------------------------------------------------------------------------
23 --
24 -- $RCSfile: cache.vhdl,v $ $Revision: 1.1 $ $Date: 2000/05/08 14:36:47 $
25 --
26 --------------------------------------------------------------------------
27 --
28 -- Entity declaration for cache.
29 --
30
31
32 use work.dlx_types.all,
33 work.mem_types.all,
34 work.cache_types.all;
35
36 entity cache is
37 generic (cache_size : positive; -- in bytes, power of 2
38 line_size : positive; -- in bytes, power of 2
39 associativity : positive; -- 1 = direct mapped
40 write_strategy : strategy_type; -- write_through or copy_back
41 Tpd_clk_out : Time; -- clock to output propagation delay
42 tag : string := "";
43 origin_x, origin_y : real := 0.0);
44 port (phi1, phi2 : in bit; -- 2-phase non-overlapping clocks
45 reset : in bit; -- synchronous reset input
46 -- connections to CPU
47 cpu_enable : in bit; -- starts memory cycle
48 cpu_width : in mem_width; -- byte/halfword/word indicator
49 cpu_write : in bit; -- selects read or write cycle
50 cpu_ready : out bit; -- status from memory system
51 cpu_a : in dlx_address; -- address bus output
52 cpu_d : inout dlx_word_bus bus; -- bidirectional data bus
53 -- connections to memory
54 mem_enable : out bit; -- starts memory cycle
55 mem_width : out mem_width; -- byte/halfword/word indicator
56 mem_write : out bit; -- selects read or write cycle
57 mem_burst : out bit; -- tell memory to burst txfer
58 mem_ready : in bit; -- status from memory system
59 mem_a : out dlx_address; -- address bus output
60 mem_d : inout dlx_word_bus bus); -- bidirectional data bus
61 end cache;
62
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