1 --------------------------------------------------------------------------
2 --
3 -- Copyright (C) 1993, Peter J. Ashenden
4 -- Mail: Dept. Computer Science
5 -- University of Adelaide, SA 5005, Australia
6 -- e-mail: petera@cs.adelaide.edu.au
7 --
8 -- This program is free software; you can redistribute it and/or modify
9 -- it under the terms of the GNU General Public License as published by
10 -- the Free Software Foundation; either version 1, or (at your option)
11 -- any later version.
12 --
13 -- This program is distributed in the hope that it will be useful,
14 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
15 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 -- GNU General Public License for more details.
17 --
18 -- You should have received a copy of the GNU General Public License
19 -- along with this program; if not, write to the Free Software
20 -- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 --
22 --------------------------------------------------------------------------
23 --
24 -- $RCSfile: dlx_test-bench_cache.vhdl,v $ $Revision: 1.1 $ $Date: 2000/05/08 14:36:48 $
25 --
26 --------------------------------------------------------------------------
27 --
28 -- Architecture for test bench for DLX and cache, including clock generator,
29 -- memory and bus monitors for both CPU/cache and cache/memory buses.
30 --
31
32
33 use std.textio.all,
34 work.dlx_types.all,
35 work.mem_types.all;
36
37
38 architecture bench_cache of dlx_test is
39
40 component clock_gen
41 port (phi1, phi2 : out bit;
42 reset : out bit);
43 end component;
44
45 component memory
46 port (phi1, phi2 : in bit;
47 a : in dlx_address;
48 d : inout dlx_word_bus bus;
49 width : in mem_width;
50 write_enable : in bit;
51 burst : in bit := '0';
52 mem_enable : in bit;
53 ready : out bit);
54 end component;
55
56 component dlx
57 port (phi1, phi2 : in bit; -- 2-phase non-overlapping clocks
58 reset : in bit; -- synchronous reset input
59 a : out dlx_address; -- address bus output
60 d : inout dlx_word_bus bus; -- bidirectional data bus
61 halt : out bit; -- halt indicator
62 width : out mem_width; -- byte/haldword/word indicator
63 write_enable : out bit; -- selects read or write cycle
64 mem_enable : out bit; -- starts memory cycle
65 ifetch : out bit; -- indicates instruction fetch
66 ready : in bit); -- status from memory system
67 end component;
68
69 component cache
70 port (phi1, phi2 : in bit; -- 2-phase non-overlapping clocks
71 reset : in bit; -- synchronous reset input
72 -- connections to CPU
73 cpu_enable : in bit; -- starts memory cycle
74 cpu_width : in mem_width; -- byte/halfword/word indicator
75 cpu_write : in bit; -- selects read or write cycle
76 cpu_ready : out bit; -- status from memory system
77 cpu_a : in dlx_address; -- address bus output
78 cpu_d : inout dlx_word_bus bus; -- bidirectional data bus
79 -- connections to memory
80 mem_enable : out bit; -- starts memory cycle
81 mem_width : out mem_width; -- byte/halfword/word indicator
82 mem_write : out bit; -- selects read or write cycle
83 mem_burst : out bit; -- tell memory to burst txfer
84 mem_ready : in bit; -- status from memory system
85 mem_a : out dlx_address; -- address bus output
86 mem_d : inout dlx_word_bus bus); -- bidirectional data bus
87 end component;
88
89 component dlx_bus_monitor
90 port (phi1, phi2 : in bit; -- 2-phase non-overlapping clocks
91 reset : in bit; -- synchronous reset
92 a : in dlx_address; -- address bus
93 d : in dlx_word; -- data bus
94 halt : in bit; -- halt indicator
95 width : in mem_width; -- byte/haldword/word indicator
96 write_enable : in bit; -- selects read or write cycle
97 burst : in bit := '0'; -- indicates more to come in burst
98 mem_enable : in bit; -- starts memory cycle
99 ifetch : in bit; -- indicates instruction fetch
100 ready : in bit); -- status from memory system
101 end component;
102
103 signal phi1, phi2, reset : bit;
104 signal cpu_a, mem_a : dlx_address;
105 signal cpu_d, mem_d : dlx_word_bus bus;
106 signal halt : bit;
107 signal cpu_width, mem_width : mem_width;
108 signal cpu_enable, mem_enable,
109 cpu_write, mem_write,
110 cpu_ready, mem_ready,
111 mem_burst, ifetch : bit;
112
113 begin
114
115 cg : clock_gen
116 port map (phi1, phi2, reset);
117
118 mem : memory
119 port map (phi1, phi2, mem_a, mem_d,
120 mem_width, mem_write, mem_burst, mem_enable, mem_ready);
121
122 proc : dlx
123 port map (phi1, phi2, reset, cpu_a, cpu_d,
124 halt, cpu_width, cpu_write, cpu_enable, ifetch, cpu_ready);
125
126 the_cache : cache
127 port map (phi1, phi2, reset,
128 cpu_enable, cpu_width, cpu_write, cpu_ready, cpu_a, cpu_d,
129 mem_enable, mem_width, mem_write, mem_burst, mem_ready, mem_a, mem_d);
130
131 cpu_cache_monitor : dlx_bus_monitor
132 port map (phi1, phi2, reset, cpu_a, cpu_d,
133 halt, cpu_width, cpu_write, open, cpu_enable, ifetch, cpu_ready);
134
135 cache_mem_monitor : dlx_bus_monitor
136 port map (phi1, phi2, reset, mem_a, mem_d,
137 halt, mem_width, mem_write, mem_burst, mem_enable, ifetch, mem_ready);
138
139 end bench_cache;
140
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