dlx/dlx_test_behaviour.vhdl

    1 --------------------------------------------------------------------------
    2 --
    3 --  Copyright (C) 1993, Peter J. Ashenden
    4 --  Mail:	Dept. Computer Science
    5 --		University of Adelaide, SA 5005, Australia
    6 --  e-mail:	petera@cs.adelaide.edu.au
    7 --
    8 --  This program is free software; you can redistribute it and/or modify
    9 --  it under the terms of the GNU General Public License as published by
   10 --  the Free Software Foundation; either version 1, or (at your option)
   11 --  any later version.
   12 --
   13 --  This program is distributed in the hope that it will be useful,
   14 --  but WITHOUT ANY WARRANTY; without even the implied warranty of
   15 --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   16 --  GNU General Public License for more details.
   17 --
   18 --  You should have received a copy of the GNU General Public License
   19 --  along with this program; if not, write to the Free Software
   20 --  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
   21 --
   22 --------------------------------------------------------------------------
   23 --
   24 --  $RCSfile: dlx_test_behaviour.vhdl,v $  $Revision: 1.1 $  $Date: 2000/05/08 14:36:48 $
   25 --
   26 --------------------------------------------------------------------------
   27 --
   28 --  Configuration of test bench for DLX, using architecture behaviour
   29 --
   30 
   31 
   32 configuration dlx_test_behaviour of dlx_test is
   33 
   34   for bench
   35 
   36     for cg : clock_gen
   37       use entity work.clock_gen(behaviour)
   38         generic map (Tpw => 8 ns, Tps => 2 ns);
   39     end for;
   40 
   41     for mem : memory
   42       use entity work.memory(behaviour)
   43         generic map (mem_size => 65536,
   44                      Tac1 => 95 ns, Tacb => 35 ns, Tpd_clk_out => 2 ns);
   45     end for;
   46 
   47     for bus_monitor : dlx_bus_monitor
   48       use entity work.dlx_bus_monitor(behaviour)
   49       generic map (enable => true, verbose => false, tag => "bus monitor");
   50     end for;
   51 
   52     for proc : dlx
   53       use entity work.dlx(behaviour)
   54         generic map (Tpd_clk_out => 2 ns, debug => true, tag => "proc");
   55     end for;
   56 
   57   end for;
   58 
   59 end dlx_test_behaviour;
   60 

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