dlx/dlx_test_instrumented.vhdl

    1 --------------------------------------------------------------------------
    2 --
    3 --  Copyright (C) 1993, Peter J. Ashenden
    4 --  Mail:	Dept. Computer Science
    5 --		University of Adelaide, SA 5005, Australia
    6 --  e-mail:	petera@cs.adelaide.edu.au
    7 --
    8 --  This program is free software; you can redistribute it and/or modify
    9 --  it under the terms of the GNU General Public License as published by
   10 --  the Free Software Foundation; either version 1, or (at your option)
   11 --  any later version.
   12 --
   13 --  This program is distributed in the hope that it will be useful,
   14 --  but WITHOUT ANY WARRANTY; without even the implied warranty of
   15 --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   16 --  GNU General Public License for more details.
   17 --
   18 --  You should have received a copy of the GNU General Public License
   19 --  along with this program; if not, write to the Free Software
   20 --  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
   21 --
   22 --------------------------------------------------------------------------
   23 --
   24 --  $RCSfile: dlx_test_instrumented.vhdl,v $  $Revision: 1.1 $  $Date: 2000/05/08 14:36:48 $
   25 --
   26 --------------------------------------------------------------------------
   27 --
   28 --  Configuration of test bench for DLX, using instrumented
   29 --  architecture of CPU and empty architecture of bus monitor.
   30 --
   31 
   32 
   33 configuration dlx_test_instrumented of dlx_test is
   34 
   35   for bench
   36 
   37     for cg : clock_gen
   38       use entity work.clock_gen(behaviour)
   39         generic map (Tpw => 8 ns, Tps => 2 ns);
   40     end for;
   41 
   42     for mem : memory
   43       use entity work.memory(behaviour)
   44         generic map (mem_size => 65536,
   45                      Tac1 => 95 ns, Tacb => 35 ns, Tpd_clk_out => 2 ns);
   46     end for;
   47 
   48     for bus_monitor : dlx_bus_monitor
   49       use entity work.dlx_bus_monitor(behaviour)
   50       generic map (enable => false);
   51     end for;
   52 
   53     for proc : dlx
   54       use entity work.dlx(instrumented)
   55         generic map (Tpd_clk_out => 2 ns, debug => false, tag => "proc");
   56     end for;
   57 
   58   end for;
   59 
   60 end dlx_test_instrumented;
   61 

This page was generated using GHDL 0.14 (20040829) [Sokcho edition], a program written by Tristan Gingold