3.2 GHDL options

Besides the options described below, GHDL passes any debugging options (those that begin with -g) and optimizations options (those that begin with -O or -f) to GCC. Refer to the GCC manual for details.

--work=NAME

Specify the name of the ‘WORK’ library. Analyzed units are always placed in the library logically named ‘WORK’. With this option, you can set its name. By default, the name is work.

GHDL checks whether ‘WORK’ is a valid identifier. Although being more or less supported, the ‘WORK’ identifier should not be an extended identifier, since the filesystem may prevent it from correctly working (due to case sensitivity or forbidden characters in filenames).

VHDL rules forbid you to add units to the ‘std’ library. Furthermore, you should not put units in the ‘ieee’ library.

--workdir=DIR

Specify the directory where the ‘WORK’ library is located. When this option is not present, the ‘WORK’ library is in the current directory. The object files created by the compiler are always placed in the same directory as the ‘WORK’ library.

Use option -P to specify where libraries other than ‘WORK’ are placed.

--std=STD

Specify the standard to use. By default, the standard is ‘93c’, which means VHDL-93 accepting VHDL-87 syntax. For details on STD values see VHDL standards.

--ieee=VER

Select the IEEE library to use. VER must be one of:

‘none’

Do not supply an IEEE library. Any library clause with the ‘IEEE’ identifier will fail, unless you have created by your own a library with the IEEE name.

‘standard’

Supply an IEEE library containing only packages defined by ieee standards. Currently, there are the multivalue logic system packages ‘std_logic_1164’ defined by IEEE 1164, the synthesis packages , ‘numeric_bit’ and ‘numeric_std’ defined by IEEE 1076.3, and the vital packages ‘vital_timing’ and ‘vital_primitives’, defined by IEEE 1076.4. The version of these packages is defined by the VHDL standard used. See VITAL packages, for more details.

‘synopsys’

Supply the former packages and the following additional packages: ‘std_logic_arith’, ‘std_logic_signed’, ‘std_logic_unsigned’, ‘std_logic_textio’. These packages were created by some companies, and are popular. However they are not standard packages, and have been placed in the IEEE library without the permission from the ieee.

‘mentor’

Supply the standard packages and the following additional package: ‘std_logic_arith’. The package is a slight variation of a definitely not standard but widely mis-used package.

To avoid errors, you must use the same IEEE library for all units of your design, and during elaboration.

-PDIRECTORY

Add DIRECTORY to the end of the list of directories to be searched for library files.

The WORK library is always searched in the path specified by the --workdir= option, or in the current directory if the latter option is not specified.

-fexplicit

When two operators are overloaded, give preference to the explicit declaration. This may be used to avoid the most common pitfall of the ‘std_logic_arith’ package. See IEEE library pitfalls, for an example.

This option is not set by default. I don't think this option is a good feature, because it breaks the encapsulation rule. When set, an operator can be silently overridden in another package. You'd better to fix your design and use the ‘numeric_std’ package.

-fpsl

Enable parsing of PSL assertions within comments. See PSL implementation, for more details.

--no-vital-checks

--vital-checks

Disable or enable checks of restriction on VITAL units. Checks are enabled by default.

Checks are performed only when a design unit is decorated by a VITAL attribute. The VITAL attributes are ‘VITAL_Level0’ and ‘VITAL_Level1’, both declared in the ‘ieee.VITAL_Timing’ package.

Currently, VITAL checks are only partially implemented. See VHDL restrictions for VITAL, for more details.

--syn-binding

Use synthesizer rules for component binding. During elaboration, if a component is not bound to an entity using VHDL LRM rules, try to find in any known library an entity whose name is the same as the component name.

This rule is known as synthesizer rule.

There are two key points: normal VHDL LRM rules are tried first and entities are searched only in known library. A known library is a library which has been named in your design.

This option is only useful during elaboration.

--PREFIX=PATH

Use PATH as the prefix path to find commands and pre-installed (std and ieee) libraries.

--GHDL1=COMMAND

Use COMMAND as the command name for the compiler. If COMMAND is not a path, then it is search in the list of program directories.

-v

Be verbose. For example, for analysis, elaboration and make commands, GHDL displays the commands executed.