The VITAL standard (partially) implemented is the IEEE 1076.4 standard published in 1995.
This standard defines restriction of the VHDL language usage on VITAL
model. A VITAL model is a design unit (entity or architecture)
decorated by the
These attributes are defined in the
Currently, only VITAL level 0 checks are implemented. VITAL level 1 models can be analyzed, but GHDL doesn't check they comply with the VITAL standard.
Moreover, GHDL doesn't check (yet) that timing generics are not read inside a VITAL level 0 model prior the VITAL annotation.
The analysis of a non-conformant VITAL model fails. You can disable the checks of VITAL restrictions with the --no-vital-checks. Even when restrictions are not checked, SDF annotation can be performed.