1 --------------------------------------------------------------------------
2 --
3 -- Copyright (C) 1993, Peter J. Ashenden
4 -- Mail: Dept. Computer Science
5 -- University of Adelaide, SA 5005, Australia
6 -- e-mail: petera@cs.adelaide.edu.au
7 --
8 -- This program is free software; you can redistribute it and/or modify
9 -- it under the terms of the GNU General Public License as published by
10 -- the Free Software Foundation; either version 1, or (at your option)
11 -- any later version.
12 --
13 -- This program is distributed in the hope that it will be useful,
14 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
15 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 -- GNU General Public License for more details.
17 --
18 -- You should have received a copy of the GNU General Public License
19 -- along with this program; if not, write to the Free Software
20 -- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 --
22 --------------------------------------------------------------------------
23 --
24 -- $RCSfile: clock_gen_test-bench.vhdl,v $ $Revision: 1.1 $ $Date: 2000/05/08 14:36:47 $
25 --
26 --------------------------------------------------------------------------
27 --
28 -- Architecture for test bench for clock generator
29 --
30
31
32 architecture bench of clock_gen_test is
33
34 component clock_gen
35 port (phi1, phi2 : out bit;
36 reset : out bit);
37 end component;
38
39 for cg : clock_gen
40 use entity work.clock_gen(behaviour)
41 generic map (Tpw => 8 ns, Tps => 2 ns);
42
43 signal p1, p2, reset : bit;
44
45 begin
46
47 cg : clock_gen
48 port map (p1, p2, reset);
49
50 end bench;
51
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