VHDL is a well-known language in EDA (Electronic Design Automation). Therefore, there are a lot of pages about VHDL. So, search engines are your friends.
The gEDA project is a collection of allied GPL'ed EDA tools. You may find some useful tools there!
For my testsuite, I used severals open source designs, written in VHDL. Some are simple, others are very complexes. Here is a list of designs:
| a DLX processor, from P.Ashenden |
| a super-scalar DLX processor |
| the LEON2/3 SPARC processor |
GHDL is certainly the most advanced free VHDL simulator, but it is not the only one.
Savant is a VHDL analysis tool. Please refer to university of Cincinnati or cliftonlabs.
FreeHDL was the first free VHDL simulator project, but it progresses very slowly.
Verilog is the other popular HDL. It has many free/open implementations.
Icarus Verilog is certainly the most popular one.
GPL Cver is a GPL version of a commercial verilog simulator. One of the most complete and supported free verilog simulator.
VeriWell Verilog simulator has recently been made open-source. It is also very complete (came from a commercial implementation).
Verilator is a Verilog translator (to C++ or SystemVerilog). It is not a full-feature verilog simulator but handles the synthesis subset very quickly.
VBS - Verilog Behavioral Simulator was written for a senior design project.
Ver is a structual Verilog compiler, but has no home page.
Copyright (C) 2004, 2005 Tristan Gingold -- tgingold AT free DOT fr
Last modified: Wed Dec 7 06:19:20 CET 2005