Unless you are only studying VHDL, you will work with bigger designs than the ones of the previous examples.
Let's see how to analyze and run a bigger design, such as the DLX model
suite written by Peter Ashenden which is distributed under the terms of the
GNU General Public License. A copy is kept on
First, untar the sources:
$ tar zxvf dlx.tar.gz
In order not to pollute the sources with the library, it is a good idea to create a work/ subdirectory for the ‘WORK’ library. To any GHDL commands, we will add the --workdir=work option, so that all files generated by the compiler (except the executable) will be placed in this directory.
$ cd dlx $ mkdir work
We will run the ‘dlx_test_behaviour’ design. We need to analyze all the design units for the design hierarchy, in the correct order. GHDL provides an easy way to do this, by importing the sources:
$ ghdl -i --workdir=work *.vhdl
and making a design:
$ ghdl -m --workdir=work dlx_test_behaviour
Before this second stage, GHDL knows all the design units of the DLX, but no one have been analyzed. The make command of GHDL analyzes and elaborates a design. This creates many files in the work/ directory, and the dlx_test_behaviour executable in the current directory.
The simulation needs to have a DLX program contained in the file dlx.out. This memory image will be be loaded in the DLX memory. Just take one sample:
$ cp test_loop.out dlx.out
And you can run the test suite:
$ ghdl -r dlx_test_behaviour
The test bench monitors the bus and displays each instruction executed. It finishes with an assertion of severity level note:
dlx-behaviour.vhdl:395:11:(assertion note): TRAP instruction encountered, execution halted
Since the clock is still running, you have to manually stop the program with the C-c key sequence. This behavior prevents you from running the test bench in batch mode. However, you may force the simulator to stop when an assertion above or equal a certain severity level occurs:
$ ghdl -r dlx_test_behaviour --assert-level=note
With this option, the program stops just after the previous message:
dlx-behaviour.vhdl:395:11:(assertion note): TRAP instruction encountered, execution halted error: assertion failed
If you want to make room on your hard drive, you can either:
$ ghdl --clean --workdir=work
This removes the executable and all the object files. If you want to rebuild the design at this point, just do the make command as shown above.
$ ghdl --remove --workdir=work
This removes the executable, all the object files and the library file. If you want to rebuild the design, you have to import the sources again, and to make the design.
$ rm -rf work
Only the executable is kept. If you want to rebuild the design, create the work/ directory, import the sources, and make the design.
Sometimes, a design does not fully follow the VHDL standards. For example it uses the badly engineered ‘std_logic_unsigned’ package. GHDL supports this VHDL dialect through some options:
See IEEE library pitfalls, for more details.